1. Field of the Invention
The present invention relates to a semiconductor integrated circuit using MOS transistors, and particularly to a body voltage controlled semiconductor integrated circuit operating with body voltages of the MOS transistors being controlled.
2. Description of Related Art
FIG. 5 is a circuit diagram showing a conventional body voltage controlled semiconductor integrated circuit. In this figure, the reference numeral 11 designates a first inverter, and 12 designates a second inverter. The first inverter 11 includes a PMOS transistor P11 and an NMOS transistor N11, in which their gates are interconnected, their drains are also interconnected, the body electrode and source electrode of the PMOS transistor P11 are connected to a power supply E11, and the body electrode and source electrode of the NMOS transistor N11 are connected to earth E.
The second inverter 12 includes a PMOS transistor P12 and an NMOS transistor N12, in which their gates are interconnected, their drains are also interconnected, their gates are connected to the output terminal of the first inverter 11 as well as to the body electrodes of the PMOS transistor P12 and NMOS transistor N12, the source electrode of the PMOS transistor P12 is connected to a power supply E12, and the source electrode of the NMOS transistor N12 is connected to the earth E. In addition, a link L12 interconnecting the drains of the two transistors of the first inverter 11 is connected to a link L13 interconnecting the gates of the two transistors of the second inverter 12.
The reference symbol "in" designates an input terminal connected to a link L11 interconnecting the gates of the PMOS transistor P11 and NMOS transistor N11, "out" designates an output terminal connected to a link L14 interconnecting the drains of the PMOS transistor P12 and NMOS transistor N12 constituting the second inverter 12, and c designates a load capacitance. Besides, the reference character G designates a gate electrode, B designates a body electrode, D designates a drain electrode and S designates a source electrode.
Next, the operation will be described. When the input terminal "in" is placed at H (high), the NMOS transistor N11 is turned on and the output of the first inverter 11 falls to L (low). Thus, the PMOS transistor P12 in the second inverter 12 is turned on, and the electric charge in the load capacitance c is absorbed to the power supply so that the output terminal "out" becomes H.
In this circuit, the PMOS transistor P11 has a characteristic as shown in FIG. 6: Its threshold voltage decreases with a decrease in the body voltage applied to its body. In contrast with this, the NMOS transistor N11 has a characteristic as shown in FIG. 7: Its threshold voltage decreases with an increase in the body voltage applied to its body. As their threshold voltage decreases, their operation is quickened. Incidentally, a related art to the conventional circuit is disclosed in Japanese patent application laid-open No. 7-86917, or U.S. Pat. No. 5,552,723.
The conventional body voltage controlled semiconductor integrated circuit with such a structure has the following problem. If a voltage above 0.8 V (built-in voltage) is applied to the second inverter 12 including the PMOS transistor P12 and NMOS transistor N12 with their gate electrodes connected to their body electrodes, a parasitic bipolar transistor composed of semiconductor layers forming the drain, body and source is turned on, and thus the transistors must operate in their saturation domain, which will retard their operation. This presents a problem in that the power supply voltage must be limited to below 0.8 V when the gate electrodes are connected to the body electrodes as in the second inverter 12. Furthermore, there is another problem that such a circuit is weak to external noise.